Packet Architects
Powering the Communication Era

At PacketArc we build high-performance Ethernet switch IP cores for packet based communication in FPGA or ASIC technology. All of our IPs are based on an in-house FlexSwitch generator. The outputs from FlexSwitch is a datasheet, C-API and verilog source code for the IP core.

• The FlexSwitch IP is primarily designed to support Ethernet Switching, IP Routing, MPLS and Software Defined Networking (SDN), but it can easily be used for any packet based processing technologies.
• We support most of the TSN protocols, and have support for MACsec and IPsec with a wide array of cryto and hashing functions.
• We have customers in Space, SOHO Networks, Enterprise Networks, Car Networks, Datacenter Networks, PON and MAN networks. Whatever type of network you build, there is a good chance Flexswitch IP has been used there before.
• The packet processing is developed in the PAC language. By using a custom language and an in-house high-level synthesis tool-flow we achieve a quick turnaround while maintaining excellent area and performance.

The switching core is built around a cell-switched shared buffer memory architecture allowing head-of-line-blocking-free switching on all ports operating at wire-speed.

Each port has queues which are controlled by a scheduler that can be as simple as a strict priority scheduler or an advanced hierarchical scheduler with WRR and traffic shapers.

Buffer memory congestion mangagement controls when packets should be accepted into queues and when they should be dropped due to congestion. This can be configured per port/queue and priority level.

For use cases where an internal buffer memory is insufficient the architecture supports an external DRAM based deep buffering.

• Unencrypted Verilog source code of IP.
• Datasheet of registers & theory of operations.
• C source code for accessing registers.
• Easy to parse YML file for register mapping.
• Verilog testbench.
• Low-level device driver.

This L2 Ethernet Switch IP Core offers a full range of features with full wirespeed on all ports plus a high speed CPU port.

The IP is compatible with ASIC technology as well as FPGA technology from most vendors.

Each port has priority queues which are controlled by a strict priority scheduler allowing the most timing critical packets to get minimal delay while providing a fairness between queues.

The switching core is built around a shared buffer memory architecture allowing head-of-line-blocking-free switching on all ports operating at wire-speed. It offers dynamic per port and per priority usage of the packet buffer memory along with buffer limiters to limit how much an egress port / priority uses of total buffer memory.

The switching core also features multiple VLAN tagging and un-tagging along with egress VLAN translation.

The L2 Ethernet Switching IP features a processor interface allowing setup of tables and register. It also features a packet based CPU port which can be used to both send and receive ethernet frames to/from the switching IP.

This IP requires no software setup to be used, it is ready to receive and forward Ethernet frames once downloaded to FPGA and connected to MACs. It has hardware learning for MAC addresses.

• Unencrypted Verilog source code of IP.
• Datasheet of registers & theory of operations.
• C source code for accessing registers.
• Easy to parse YML file for register mapping.
• Verilog testbench.
• Low-level device driver.

This L3 Ethernet Switch/Router IP core is built around a shared buffer memory architecture providing wire-speed switching and routing on all ports without head of line blocking. It offers dynamic allocation of packet buffers per port and priority to avoid starvation due to over-allocation. Advanced QoS features allow the most timing critical packets to get minimal delay while providing fairness between traffic classes.

No initial software setup is required and due to the hardware learning for MAC addresses the core is ready to receive and forward Ethernet frames immediately once powered up. There is a high performance processor interface for register configuration, and a high performance dedicated CPU port for slow path processing of packets.

The design is optimized for both FPGA and ASIC technology but does not have any dependencies on the underlying technology. If the target technology has TCAMs these can be utilized.

This is a L2 switch and an IP/MPLS router with advanced ACL engines.

It has support for IEEE 1588 when combined with the approriate MACs.

QoS functions includes DiffServ SrTCM/TrTCM ingress admission control, shapers and WRR schedulers.

This core supports wire speed tunnel entry and tunnel exit.

There are support for ingress and egress Network Address Translation (NAT)